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Bobcat / Nehalem Processors Chart

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This list is not comprehensive.

AMD Desktop | Intel Desktop

AMD Desktop


Phenom II (Socket AM3)
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Athlon II X2 250u MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE)
2010		938 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 260u MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
2010		938 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 270u MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
3Q 2010		938 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 215 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
3Q 2009		938 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 220 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
3Q 2010		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 235e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$69}		938 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 240e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$77}		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 240 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
July 23, 2009 - {$60}		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 245e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
May 10, 2010 - {$77}		938 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 245 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
July 23, 2009 - {$66} 		938 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 250e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
September 21, 2010		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 250 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
June 2, 2009 - {$87}		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 255 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
January 25, 2010 - {$74}		938 pins
3100MHz (200x15.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 260 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
May 10, 2010 - {$76}		938 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 265 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
September 21, 2010 - {$76}		938 pins
3300MHz (200x16.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X3 400e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$97}		938 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 405e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$102}		938 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 415e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
May 10, 2010 - {$102}		938 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 420e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
September 21, 2010		938 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 425 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$76}		938 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 425e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
2011?		938 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 435 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$87}		938 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 440 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
January 25, 2009 - {$84}		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 445 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
May 10, 2010 - {$87}		938 pins
3100MHz (200x15.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 450 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
September 21, 2010 - {$87}		938 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 455 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
December 7, 2010 - {$87}		938 pins
3300MHz (200x16.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 460 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
2011 - {$87}		938 pins
3400MHz (200x17)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 600e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$133}		938 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 605e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$143}		938 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 610e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
May 10, 2010 - {$145}		938 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 615e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
September 21, 2010		938 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 620 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
September 16, 2009 - {$99}		938 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 630 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
September 16, 2009 - {$122}		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 635 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
January 25, 2010 - {$119}		938 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 640 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
May 10, 2010 - {$122}		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 645 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
September 21, 2010 - {$122}		938 pins
3100MHz (200x15.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 650 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
2011		938 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 665 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
[not released]		938 pins
3300MHz (200x16.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Phenom II X2 545 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
June 2, 2009		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X2 550 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
June 2, 2009 - {$102}		938 pins
3100MHz (200x15.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X2 555 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
January 25, 2010 - {$99}		938 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X2 560 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
September 21, 2010 - {$105}		938 pins
3300MHz (200x16.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X2 565 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
December 7, 2010 - {$115}		938 pins
3400MHz (200x17)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X2 570 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
May 3, 2011		938 pins
3500MHz (200x17.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X3 700e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
June 2, 2009		938 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X3 705e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
June 2, 2009 - {$125}		938 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X3 710 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
February 9, 2009 - {$125}		938 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X3 720 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
February 9, 2009 - {$145}		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X4 805 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
February 9, 2009		938 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 810 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
February 9, 2009 - {$175}		938 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 820 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
1Q 2010		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 840 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
January 4, 2011 - {$102}		938 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 900e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
June 2, 2009		938 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 905e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
June 2, 2009 - {$195}		938 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 910 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
February 9, 2009		938 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 910e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
January 25, 2010 - {$169}		938 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 920 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
[not released]		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 925 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
2009		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 945 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
April 23, 2009 - {$225}		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 950 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
[not released]		938 pins
3100MHz (200x15.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 955 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
April 23, 2009 - {$245}		938 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 960 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
[not released]		938 pins
3300MHz (200x16.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 965 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
August 13, 2009 - {$245}		938 pins
3400MHz (200x17)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 970 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
September 21, 2010 - {$185}		938 pins
3500MHz (200x17.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 975 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
January 4, 2011 - {$195}		938 pins
3600MHz (200x18)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 980 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
May 3, 2011 - {$185}		938 pins
3700MHz (200x18.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 960T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Zosma)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V, Turbo)
[cancelled]		938 pins
3000MHz (200x15)
(3.4GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1035T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
February 1, 2011		938 pins
2600MHz (200x13)
(3.1GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1045T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
2011		938 pins
2700MHz (200x13.5)
(3.2GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1055T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
April 27, 2010 - {$199}		938 pins
2800MHz (200x14)
(3.3GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1065T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
February 1, 2011 - {$185}		938 pins
2900MHz (200x14.5)
(3.4GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1075T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
September 21, 2010 - {$245}		938 pins
3000MHz (200x15)
(3.5GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1090T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
April 27, 2010 - {$295}		938 pins
3200MHz (200x16)
(3.6GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1100T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
December 7, 2010 - {$265}		938 pins
3300MHz (200x16.5)
(3.7GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Sempron 140 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Sargas)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(HT 3.0, DICE, AMD-V)
July 23, 2009 - {$36}		938 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Sempron 145 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Sargas)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(HT 3.0, DICE, AMD-V)
3Q 2010 - {$36}		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Sempron 150 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Sargas)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(HT 3.0, DICE, AMD-V)
February 1, 2011		938 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Sempron 180 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Sargas)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(HT 3.0, DICE, AMD-V)
[not released]		938 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die


Business-Class Athlon / Phenom
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Athlon 1640B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
April 28, 2008 - {$50}		940 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 4450B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
April 28, 2008 - {$85}		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 4850B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
August 18, 2008		940 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 5000B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
April 28, 2008 - {$95}		940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.375v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 5200B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
April 28, 2008 - {$110}		940 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
1.375v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 5400B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
April 28, 2008 - {$120}		940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 5600B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
August 18, 2008		940 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon II X2 B22 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
3Q 2009		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 B24 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
3Q 2009		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 B53 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
3Q 2009		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Athlon II X2 B55 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
3Q 2009		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Athlon II X3 B73 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
3Q 2009		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Athlon II X3 B75 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
3Q 2009		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Athlon II X4 B93 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
3Q 2009		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Athlon II X4 B95 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
3Q 2009		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom X3 8600B MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
April 28, 2008 - {$175}		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (?-way)		463 million
0.065µm process
288mm² die
Phenom X3 8750B MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
August 18, 2008		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v		Socket AM2+3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (?-way)		463 million
0.065µm process
288mm² die
Phenom X4 9600B MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
April 28, 2008 - {$230}		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (?-way)		463 million
0.065µm process
288mm² die
Phenom X4 9750B MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
August 18, 2008		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (?-way)		463 million
0.065µm process
288mm² die


Athlon 64 FX
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Athlon 64 FX-51 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
September 23, 2003 - {$733}		940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v		Socket 94064KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die
Athlon 64 FX-53 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
March 18, 2004 - {$733}		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		Socket 94064KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die
Athlon 64 FX-53 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
June 1, 2004 - {$799}		939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		Socket 93964KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die
Athlon 64 FX-55 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
October 19, 2004 - {$827}		939 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.5v		Socket 93964KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die
Athlon 64 FX-57 MMX 3DNow! SSE SSE2 SSE3
(San Diego)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
June 27, 2005 - {$1031}		939 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		Socket 93964KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		114 million
0.09µm process
115mm² die
Athlon 64 FX-60 MMX 3DNow! SSE SSE2 SSE3
(Toledo)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
January 10, 2006 - {$1031}		939 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.35v		Socket 9392x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		233 million
0.09µm process
~199mm² die
Athlon 64 FX-62 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 mem controller, AMD-V)
(dual core)
May 23, 2006 - {$1031}		940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 FX-70 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(dual core)
November 30, 2006 - {$599}		1207 balls
2600MHz (200x13)
(64-bit dual-pumped bus)
1.4v		Socket F2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 FX-72 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(dual core)
November 30, 2006 - {$799}		1207 balls
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		Socket F2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 FX-74 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
November 30, 2006 - {$999}		1207 balls
3000MHz (200x15)
(64-bit dual-pumped bus)
1.4v		Socket F2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 FX-76 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
[not released]		1207 balls
3200MHz (200x16)
(64-bit dual-pumped bus)
1.4v		Socket F2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Phenom FX-80 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena FX)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
[cancelled]		1207 balls
2200MHz (200x11)
(64-bit dual-pumped bus)
?v		Socket F+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom FX-??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb FX)
(128-bit on-Die unbuffered DDR3 PC? mem controller, AMD-V)
(quad core, HT 3.0, DICE)
[cancelled]		? pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket AM34x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
?MB on-Die shared L3 (32-way)		? million
0.045µm process
?mm² die


FX
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
FX 4100 MMX 3DNow! SSE SSE2 SSE3 SSE4.2 AVX
(Zambezi)
(128-bit on-Die unbuffered DDR3 PC14933 mem controller)
(quad core, HT 3.0, DICE, AMD-V, Turbo)
October 12, 2011 - {$115}		942 pins
3600MHz (200x18)
(3.8GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM3+4x 16KB data (4-way)
2x 64KB shared instruction (2-way)
2x 2MB on-Die shared L2 (16-way)
8MB on-Die shared L3 (64-way)		~1200 million
0.032µm process
315mm² die
FX 4130 MMX 3DNow! SSE SSE2 SSE3 SSE4.2 AVX
(Zambezi)
(128-bit on-Die unbuffered DDR3 PC14933 mem controller)
(quad core, HT 3.0, DICE, AMD-V, Turbo)
August 27, 2012 - {$112}		942 pins
3800MHz (200x19)
(3.9GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM3+4x 16KB data (4-way)
2x 64KB shared instruction (2-way)
2x 2MB on-Die shared L2 (16-way)
4MB on-Die shared L3 (64-way)		~1200 million
0.032µm process
315mm² die
FX 4170 MMX 3DNow! SSE SSE2 SSE3 SSE4.2 AVX
(Zambezi)
(128-bit on-Die unbuffered DDR3 PC14933 mem controller)
(quad core, HT 3.0, DICE, AMD-V, Turbo)
February 28, 2012 - {$135}		942 pins
4200MHz (200x21)
(4.3GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM3+4x 16KB data (4-way)
2x 64KB shared instruction (2-way)
2x 2MB on-Die shared L2 (16-way)
8MB on-Die shared L3 (64-way)		~1200 million
0.032µm process
315mm² die
FX 6100 MMX 3DNow! SSE SSE2 SSE3 SSE4.2 AVX
(Zambezi)
(128-bit on-Die unbuffered DDR3 PC14933 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
October 12, 2011 - {$165}		942 pins
3300MHz (200x16.5)
(3.9GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM3+6x 16KB data (4-way)
3x 64KB shared instruction (2-way)
3x 2MB on-Die shared L2 (16-way)
8MB on-Die shared L3 (64-way)		~1200 million
0.032µm process
315mm² die
FX 6200 MMX 3DNow! SSE SSE2 SSE3 SSE4.2 AVX
(Zambezi)
(128-bit on-Die unbuffered DDR3 PC14933 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
February 28 2012 - {$165}		942 pins
3800MHz (200x19)
(4.1GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM3+6x 16KB data (4-way)
3x 64KB shared instruction (2-way)
3x 2MB on-Die shared L2 (16-way)
8MB on-Die shared L3 (64-way)		~1200 million
0.032µm process
315mm² die
FX 8120 MMX 3DNow! SSE SSE2 SSE3 SSE4.2 AVX
(Zambezi)
(128-bit on-Die unbuffered DDR3 PC14933 mem controller)
(8 cores, HT 3.0, DICE, AMD-V, Turbo)
October 12, 2011 - {$205}		942 pins
3100MHz (200x15.5)
(4.0GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM3+8x 16KB data (4-way)
4x 64KB shared instruction (2-way)
4x 2MB on-Die shared L2 (16-way)
8MB on-Die shared L3 (64-way)		~1200 million
0.032µm process
315mm² die
FX 8150 MMX 3DNow! SSE SSE2 SSE3 SSE4.2 AVX
(Zambezi)
(128-bit on-Die unbuffered DDR3 PC14933 mem controller)
(8 cores, HT 3.0, DICE, AMD-V, Turbo)
October 12, 2011 - {$245}		942 pins
3600MHz (200x18)
(4.2GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM3+8x 16KB data (4-way)
4x 64KB shared instruction (2-way)
4x 2MB on-Die shared L2 (16-way)
8MB on-Die shared L3 (64-way)		~1200 million
0.032µm process
315mm² die


APUs (Bobcat)
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
C-30 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Ontario)
(64-bit on-Die unbuffered DDR3 PC12800 mem controller)
(Radeon 6250 HD APU)
January 4, 2011		413 balls
1200MHz (200x6)
(64-bit dual-pumped bus)
?v		Socket FT132KB data (2-way)
32KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
?mm² die
C-50 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Ontario)
(64-bit on-Die unbuffered DDR3 PC12800 mem controller)
(dual core, Radeon 6250 HD APU)
January 4, 2011		413 balls
1000MHz (200x5)
(64-bit dual-pumped bus)
?v		Socket FT12x 32KB data (2-way)
2x 32KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
?mm² die
C-60 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Ontario)
(64-bit on-Die unbuffered DDR3 PC12800 mem controller)
(dual core, Radeon 6320 HD APU)
August 22, 2011		413 balls
1000MHz (200x5)
(64-bit dual-pumped bus)
?v		Socket FT12x 32KB data (2-way)
2x 32KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
?mm² die
E-240 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Zacate)
(64-bit on-Die unbuffered DDR3 PC8500 mem controller)
(Radeon HD 6310 APU)
January 4, 2011		413 balls
1500MHz (200x7.5)
(64-bit dual-pumped bus)
?v		Socket FT132KB data (2-way)
32KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
75mm² die
E-300 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Zacate)
(64-bit on-Die unbuffered DDR3 PC8500 mem controller)
(dual core, Radeon HD 6310 APU)
August 22, 2011		413 balls
1300MHz (200x6.5)
(64-bit dual-pumped bus)
?v		Socket FT12x 32KB data (2-way)
2x 32KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
75mm² die
E-350 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Zacate)
(64-bit on-Die unbuffered DDR3 PC8500 mem controller)
(dual core, Radeon HD 6310 APU)
January 4, 2011		413 balls
1600MHz (200x8)
(64-bit dual-pumped bus)
?v		Socket FT12x 32KB data (2-way)
2x 32KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
75mm² die
E-450 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Zacate)
(64-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, Radeon HD 6320 APU)
August 22, 2011		413 balls
1600MHz (200x8)
(64-bit dual-pumped bus)
?v		Socket FT12x 32KB data (2-way)
2x 32KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
75mm² die
E1-1200 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Zacate)
(64-bit on-Die unbuffered DDR3 PC8500 mem controller)
(dual core, Radeon HD 7310 APU)
June 15, 2012		413 balls
1400MHz (200x7)
(64-bit dual-pumped bus)
?v		Socket FT12x 32KB data (2-way)
2x 32KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
75mm² die
E2-1800 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Zacate)
(64-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, Radeon HD 7340 APU)
June 15, 2012		413 balls
1700MHz (200x8.5)
(64-bit dual-pumped bus)
?v		Socket FT12x 32KB data (2-way)
2x 32KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
75mm² die


APUs (Socket FM1)
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Athlon II X4 631 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core)
August 2011 - {$79}		905 balls
2600MHz (100x26)
(64-bit dual-pumped bus)
?v		Socket FM14x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
Athlon II X4 638 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core)
February 2012 - {$81}		905 balls
2700MHz (100x27)
(64-bit dual-pumped bus)
?v		Socket FM14x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
Athlon II X4 641 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core)
February 2012 - {$81}		905 balls
2800MHz (100x28)
(64-bit dual-pumped bus)
?v		Socket FM14x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
Athlon II X4 651 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core)
November 16, 2011 - {$92}		905 balls
3000MHz (100x30)
(64-bit dual-pumped bus)
?v		Socket FM14x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
E2-3200 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(dual core, Radeon 6379D APU)
September, 2011		905 balls
2400MHz (100x24)
(64-bit dual-pumped bus)
?v		Socket FM12x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
A4-3300 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(dual core, Radeon 6410D APU)
September 7, 2011 - {$64}		905 balls
2500MHz (100x25)
(64-bit dual-pumped bus)
?v		Socket FM12x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
A4-3400 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(dual core, Radeon 6410D APU)
September 7, 2011 - {$69}		905 balls
2700MHz (100x27)
(64-bit dual-pumped bus)
?v		Socket FM12x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
A4-3420 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(dual core, Radeon 6410D APU)
December 20, 2011		905 balls
2800MHz (100x28)
(64-bit dual-pumped bus)
?v		Socket FM12x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
A6-3500 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(tri core, Radeon 6530D APU, Turbo)
August 17, 2011 - {$89}		905 balls
2100MHz (100x21)
(2.4GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket FM13x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
A6-3600 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core, Radeon 6530D APU, Turbo)
August, 2011 - {$109}		905 balls
2100MHz (100x21)
(2.4GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket FM14x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
A6-3620 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core, Radeon 6530D APU, Turbo)
December 20, 2011		905 balls
2200MHz (100x22)
(2.5GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket FM14x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
A6-3650 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core, Radeon 6530D APU)
June 30, 2011 - {$115}		905 balls
2600MHz (100x26)
(64-bit dual-pumped bus)
?v		Socket FM14x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
A6-3670K MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core, Radeon 6530D APU)
December 20, 2011 - {$115}		905 balls
2700MHz (100x27)
(64-bit dual-pumped bus)
?v		Socket FM14x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
A8-3800 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core, Radeon 6550D APU, Turbo)
August, 2011 - {$129}		905 balls
2400MHz (100x24)
(2.7GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket FM14x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
A8-3820 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core, Radeon 6550D APU, Turbo)
December 20, 2011		905 balls
2500MHz (100x25)
(2.8GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket FM14x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
A8-3850 MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core, Radeon 6550D APU)
June 30, 2011 - {$135}		905 balls
2900MHz (100x29)
(64-bit dual-pumped bus)
?v		Socket FM14x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
A8-3870K MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core, Radeon 6550D APU)
December 20, 2011 - {$135}		905 balls
3000MHz (100x30)
(64-bit dual-pumped bus)
?v		Socket FM14x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		~1000 million
0.032µm process
228mm² die
??? MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Krishna)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(? core, APU)
[cancelled]		905 balls
?MHz (100x?)
(64-bit dual-pumped bus)
?v		Socket FM1?x 32KB data (2-way)
?x 32KB instruction (2-way)
?x 512KB on-Die unified L2 (16-way exclusive)		? million
0.028µm process
?mm² die
??? MMX 3DNow! SSE SSE2 SSE3 SSE4.2
(Wichita)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(quad core, APU, Turbo)
[cancelled]		? balls
?MHz (100x?)
(?GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket FT24x 32KB data (2-way)
4x 32KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		? million
0.028µm process
?mm² die


Intel Desktop


Core i7 (Nehalem)
Intel
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Pentium G6950 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(533MHz Intel HD GPU, dual core)
(EM64T, NX bit, VT)
January 7, 2010 - {$87}		1156 balls
2800MHz (133x21)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Pentium G6960 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(533MHz Intel HD GPU, dual core)
(EM64T, NX bit, VT)
January 9, 2011 - {$89}		1156 balls
2933MHz (133x22)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i3 530 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT)
January 7, 2010 - {$113}		1156 balls
2933MHz (133x22)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i3 540 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT)
January 7, 2010 - {$133}		1156 balls
3066MHz (133x23)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i3 550 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT)
May 31, 2010 - {$138}		1156 balls
3200MHz (133x24)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i3 560 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT)
August 30, 2010 - {$138}		1156 balls
3333MHz (133x25)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i5 ??? MMX SSE SSE2 SSE3 SSE4.2
(Havendale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(GPU, dual core, SMT Hyperthreading, EM64T, NX bit, VT)
[cancelled]		1156 balls
?MHz (133x?)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		? million
0.045µm process
?mm² die
? million GPU {0.045µm - ?mm²}
Core i5 650 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
January 7, 2010 - {$176}		1156 balls
3200MHz (133x24)
(3.46GHz Turbo)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i5 655K MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
May 28, 2010 - {$216}		1156 balls
3200MHz (133x24)
(3.46GHz Turbo)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i5 660 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
January 7, 2010 - {$196}		1156 balls
3333MHz (133x25)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i5 661 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(900MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
January 7, 2010 - {$196}		1156 balls
3333MHz (133x25)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i5 670 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
January 7, 2010 - {$284}		1156 balls
3466MHz (133x26)
(3.73GHz Turbo)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i5 680 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
April 19, 2010 - {$294}		1156 balls
3600MHz (133x27)
(3.86GHz Turbo)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i5 750 MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, EM64T, NX bit, VT, TXT, Turbo)
September 8, 2009 - {$196}		1156 balls
2666MHz (133x20)
(3.2GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i5 750S MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, EM64T, NX bit, VT, TXT, Turbo)
January 7, 2010 - {$259}		1156 balls
2400MHz (133x18)
(3.2GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i5 760 MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, EM64T, NX bit, VT, TXT, Turbo)
July 19, 2010 - {$205}		1156 balls
2800MHz (133x21)
(3.33GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i7 860 MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
September 8, 2009 - {$284}		1156 balls
2800MHz (133x21)
(3.46GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i7 860S MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
January 9, 2010 - {$337}		1156 balls
2800MHz (133x21)
(3.46GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i7 870 MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
September 8, 2009 - {$562}		1156 balls
2933MHz (133x22)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i7 870S MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
July 19, 2010 - {$351}		1156 balls
2666MHz (133x20)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i7 875K MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
May 28, 2010 - {$342}		1156 balls
2933MHz (133x22)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i7 880 MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
May 31, 2010 - {$583}		1156 balls
3066MHz (133x23)
(3.73GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i7 920 MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
November 17, 2008 - {$284}		1366 balls
2666MHz (133x20)
(2.93GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
263mm² die
Core i7 930 MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
March 1, 2010 - {$294}		1366 balls
2800MHz (133x21)
(3.06GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
263mm² die
Core i7 940 MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
November 17, 2008 - {$562}		1366 balls
2933MHz (133x22)
(3.2GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
263mm² die
Core i7 950 MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
June 3, 2009 - {$562}		1366 balls
3066MHz (133x23)
(3.33GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
263mm² die
Core i7 960 MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
October 18, 2009 - {$562}		1366 balls
3200MHz (133x24)
(3.46GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
263mm² die
Core i7 ??? MMX SSE SSE2 SSE3 SSE4.2
(Gulftown)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 2xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
[not released]		1366 balls
?MHz (?x?)
(?GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
?MB on-Die shared L3 (16-way)		1170 million
0.032µm process
240mm² die
Intel
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Core i7 965 Extreme MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
November 17, 2008 - {$999}		1366 balls
3200MHz (133x24)
(3.46GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
263mm² die
Core i7 975 Extreme MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
June 3, 2009 - {$999}		1366 balls
3333MHz (133x25)
(3.6GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
263mm² die
Core i7 970 MMX SSE SSE2 SSE3 SSE4.2
(Gulftown)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(6 cores, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
July 19, 2010 - {$885}		1366 balls
3200MHz (133x24)
(3.46GHz Turbo)
(64-bit QPI)
?v		Socket 13666x 32KB data (8-way)
6x 32KB instruction (4-way)
6x 256KB on-Die unified L2 (8-way)
12MB on-Die shared L3 (16-way)		1170 million
0.032µm process
240mm² die
Core i7 980X Extreme MMX SSE SSE2 SSE3 SSE4.2
(Gulftown)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(6 cores, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
March 15, 2010 - {$999}		1366 balls
3333MHz (133x25)
(3.6GHz Turbo)
(64-bit QPI)
?v		Socket 13666x 32KB data (8-way)
6x 32KB instruction (4-way)
6x 256KB on-Die unified L2 (8-way)
12MB on-Die shared L3 (16-way)		1170 million
0.032µm process
240mm² die
Core i7 990X Extreme MMX SSE SSE2 SSE3 SSE4.2
(Gulftown)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(6 cores, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
February 14, 2011 - {$999}		1366 balls
3466MHz (133x26)
(3.73GHz Turbo)
(64-bit QPI)
?v		Socket 13666x 32KB data (8-way)
6x 32KB instruction (4-way)
6x 256KB on-Die unified L2 (8-way)
12MB on-Die shared L3 (16-way)		1170 million
0.032µm process
240mm² die


Core i7 (Socket 1155)
Intel
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Celeron G440 MMX SSE SSE2 SSE3 SSE4.2
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(650MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
September 5, 2011 - {$37}		1155 balls
1600MHz (100x16)
(64-bit bus)
?v		Socket 115532KB data (8-way)
32KB instruction (8-way)
1.5k µops instruction (8-way)
256KB on-Die unified L2 (8-way)
1MB on-Die shared L3 (12-way)		? million
0.032µm process
?mm² die
Celeron G460 MMX SSE SSE2 SSE3 SSE4.2
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(650MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
4Q 2011		1155 balls
1800MHz (100x18)
(64-bit bus)
?v		Socket 115532KB data (8-way)
32KB instruction (8-way)
1.5k µops instruction (8-way)
256KB on-Die unified L2 (8-way)
1.5MB on-Die shared L3 (12-way)		? million
0.032µm process
?mm² die
Celeron G465 MMX SSE SSE2 SSE3 SSE4.2
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(650MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
September 3, 2012 - {$37}		1155 balls
1900MHz (100x19)
(64-bit bus)
?v		Socket 115532KB data (8-way)
32KB instruction (8-way)
1.5k µops instruction (8-way)
256KB on-Die unified L2 (8-way)
1.5MB on-Die shared L3 (12-way)		? million
0.032µm process
?mm² die
Celeron G470 MMX SSE SSE2 SSE3 SSE4.2
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(650MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
June 10, 2013 - {$37}		1155 balls
2000MHz (100x20)
(64-bit bus)
?v		Socket 115532KB data (8-way)
32KB instruction (8-way)
1.5k µops instruction (8-way)
256KB on-Die unified L2 (8-way)
1.5MB on-Die shared L3 (12-way)		? million
0.032µm process
?mm² die
Celeron G530 MMX SSE SSE2 SSE3 SSE4.2
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
September 5, 2011 - {$42}		1155 balls
2400MHz (100x24)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
2MB on-Die shared L3 (12-way)		? million
0.032µm process
?mm² die
Celeron G530T MMX SSE SSE2 SSE3 SSE4.2
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(dual core, 650MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
September 5, 2011 - {$47}		1155 balls
2000MHz (100x20)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
2MB on-Die shared L3 (12-way)		? million
0.032µm process
?mm² die
Celeron G540 MMX SSE SSE2 SSE3 SSE4.2
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
September 5, 2011 - {$52}		1155 balls
2500MHz (100x25)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
2MB on-Die shared L3 (12-way)		? million
0.032µm process
?mm² die
Celeron G540T MMX SSE SSE2 SSE3 SSE4.2
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(dual core, 650MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
June 4, 2012 - {$42}		1155 balls
2100MHz (100x21)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
2MB on-Die shared L3 (12-way)		? million
0.032µm process
?mm² die
Celeron G550 MMX SSE SSE2 SSE3 SSE4.2
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
June 4, 2012 - {$52}		1155 balls
2600MHz (100x26)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
2MB on-Die shared L3 (12-way)		? million
0.032µm process
?mm² die
Celeron G550T MMX SSE SSE2 SSE3 SSE4.2
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(dual core, 650MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
September 3, 2012 - {$42}		1155 balls
2200MHz (100x22)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
2MB on-Die shared L3 (12-way)		? million
0.032µm process
?mm² die
Celeron G555 MMX SSE SSE2 SSE3 SSE4.2
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
September 3, 2012 - {$52}		1155 balls
2700MHz (100x27)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
2MB on-Die shared L3 (12-way)		? million
0.032µm process
?mm² die
Celeron G1610 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT)
January 21, 2013 - {$42}		1155 balls
2600MHz (100x26)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
2MB on-Die shared L3 (16-way)		? million
0.022µm process
94mm² die
Celeron G1610T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT)
January 21, 2013 - {$42}		1155 balls
2300MHz (100x23)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
2MB on-Die shared L3 (16-way)		? million
0.022µm process
94mm² die
Celeron G1620 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT)
January 21, 2013 - {$52}		1155 balls
2700MHz (100x27)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
2MB on-Die shared L3 (16-way)		? million
0.022µm process
94mm² die
Pentium G620 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
May 23, 2011 - {$64}		1155 balls
2600MHz (100x26)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G620T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
May 23, 2011 - {$70}		1155 balls
2200MHz (100x22)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G622 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
2Q, 2011		1155 balls
2600MHz (100x26)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G630 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
September 5, 2011 - {$75}		1155 balls
2700MHz (100x27)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G630T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
September 5, 2011 - {$70}		1155 balls
2300MHz (100x23)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G640 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
June 4, 2012 - {$64}		1155 balls
2800MHz (100x28)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G640T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
June 4, 2012 - {$64}		1155 balls
2400MHz (100x24)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G645 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
September 3, 2012 - {$64}		1155 balls
2900MHz (100x29)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G645T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
September 3, 2012 - {$64}		1155 balls
2500MHz (100x25)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G840 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
May 23, 2011 - {$75}		1155 balls
2800MHz (100x28)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G850 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
May 23, 2011 - {$86}		1155 balls
2900MHz (100x29)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G860 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
September 5, 2011 - {$86}		1155 balls
3000MHz (100x30)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G860T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
June 4, 2012 - {$75}		1155 balls
2600MHz (100x26)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G870 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
June 4, 2012 - {$86}		1155 balls
3000MHz (100x30)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Pentium G2010 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT)
January 22, 2013 - {$64}		1155 balls
2800MHz (100x28)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (16-way)		? million
0.022µm process
?mm² die
Pentium G2020 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT)
January 22, 2013 - {$64}		1155 balls
2900MHz (100x29)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (16-way)		? million
0.022µm process
?mm² die
Pentium G2020T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT)
January 22, 2013 - {$64}		1155 balls
2500MHz (100x25)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (16-way)		? million
0.022µm process
?mm² die
Pentium G2030 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT)
June 10, 2013 - {$64}		1155 balls
3000MHz (100x30)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (16-way)		? million
0.022µm process
?mm² die
Pentium G2030T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT)
June 10, 2013		1155 balls
2600MHz (100x26)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (16-way)		? million
0.022µm process
?mm² die
Pentium G2100T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT)
September 3, 2012 - {$75}		1155 balls
2600MHz (100x26)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		? million
0.022µm process
?mm² die
Pentium G2120 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT)
September 3, 2012 - {$86}		1155 balls
3100MHz (100x31)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		? million
0.022µm process
?mm² die
Pentium G2120T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT)
June 10, 2013 - {$75}		1155 balls
2700MHz (100x27)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		? million
0.022µm process
?mm² die
Pentium G2130 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT)
January 22, 2013 - {$86}		1155 balls
3200MHz (100x32)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (16-way)		? million
0.022µm process
?mm² die
Pentium G2140 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT)
June 10, 2013 - {86}		1155 balls
3300MHz (100x33)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (16-way)		? million
0.022µm process
?mm² die
Core i3 2100 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
February 20, 2011 - {$117}		1155 balls
3100MHz (100x31)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Core i3 2100T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
February 20, 2011 - {$127}		1155 balls
2500MHz (100x25)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Core i3 2102 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
2Q, 2011		1155 balls
3100MHz (100x31)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Core i3 2105 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 3000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
May 23, 2011 - {$134}		1155 balls
3100MHz (100x31)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		624 million
0.032µm process
149mm² die
Core i3 2120 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
February 20, 2011 - {$138}		1155 balls
3300MHz (100x33)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Core i3 2120T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
September 5, 2011 - {$127}		1155 balls
2600MHz (100x26)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Core i3 2125 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 3000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
September 5, 2011 - {$134}		1155 balls
3300MHz (100x33)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		624 million
0.032µm process
149mm² die
Core i3 2130 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
September 5, 2011 - {$138}		1155 balls
3400MHz (100x34)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		504 million
0.032µm process
131mm² die
Core i3 3210 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
January 21, 2013 - {$117}		1155 balls
3200MHz (100x32)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		? million
0.022µm process
94mm² die
Core i3 3220 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
September 3, 2012 - {$117}		1155 balls
3300MHz (100x33)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		? million
0.022µm process
94mm² die
Core i3 3220T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
September 3, 2012 - {$117}		1155 balls
2800MHz (100x28)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		? million
0.022µm process
94mm² die
Core i3 3225 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(dual core, 650MHz Intel HD 4000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
September 3, 2012 - {$134}		1155 balls
3300MHz (100x33)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		? million
0.022µm process
94mm² die
Core i3 3240 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
September 3, 2012 - {$138}		1155 balls
3400MHz (100x34)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		? million
0.022µm process
94mm² die
Core i3 3240T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
September 3, 2012 - {$138}		1155 balls
2900MHz (100x29)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		? million
0.022µm process
94mm² die
Core i3 3245 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(dual core, 650MHz Intel HD 4000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
June 10, 2013 - {$134}		1155 balls
3400MHz (100x34)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		? million
0.022µm process
94mm² die
Core i3 3250 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
June 10, 2013 - {$138}		1155 balls
3500MHz (100x35)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		? million
0.022µm process
94mm² die
Core i3 3250T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge M-2)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
June 10, 2013 - {$138}		1155 balls
3000MHz (100x30)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (12-way)		? million
0.022µm process
94mm² die
Core i5 2390T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
February 20, 2011 - {$195}		1155 balls
2700MHz (100x27)
(3.5GHz Turbo)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		504 million
0.032µm process
131mm² die
Core i5 2300 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, Turbo)
January 9, 2011 - {$177}		1155 balls
2800MHz (100x28)
(3.1GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 2310 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, Turbo)
May 23, 2011 - {$177}		1155 balls
2900MHz (100x29)
(3.2GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 2320 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, Turbo)
September 5, 2011 - {$177}		1155 balls
3000MHz (100x30)
(3.2GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 2380P MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, Turbo)
January 30, 2012 - {$177}		1155 balls
3100MHz (100x31)
(?GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 2400 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$184}		1155 balls
3100MHz (100x31)
(3.4GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 2400S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$195}		1155 balls
2500MHz (100x25)
(3.3GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 2405S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 3000 GPU)
(EM64T, NX bit, VT, TXT, Turbo)
May 23, 2011 - {$205}		1155 balls
2500MHz (100x25)
(3.3GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 2450P MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, Turbo)
January 30, 2012 - {$195}		1155 balls
3200MHz (100x32)
(?GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 2500 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$205}		1155 balls
3300MHz (100x33)
(3.7GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 2500K MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, Turbo)
January 9, 2011 - {$216}		1155 balls
3300MHz (100x33)
(3.7GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 2500S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$216}		1155 balls
2700MHz (100x27)
(3.7GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 2500T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$216}		1155 balls
2300MHz (100x23)
(3.3GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 2550K MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, Turbo)
January 30, 2012 - {$225}		1155 balls
3400MHz (100x34)
(?GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i5 3470T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(dual core, 650MHz Intel HD 2500 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, vPro, Turbo)
June 4, 2012 - {$184}		1155 balls
2.9MHz (100x29)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3330 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT, Turbo)
September 3, 2012 - {$182}		1155 balls
3000MHz (100x30)
(3.2GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3330S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT, Turbo)
September 3, 2012 - {$177}		1155 balls
2700MHz (100x27)
(3.2GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3335S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 4000 GPU)
(EM64T, NX bit, VT, Turbo)
September 3, 2012 - {$177}		1155 balls
2700MHz (100x27)
(3.2GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3350P MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, EM64T, NX bit, VT, Turbo)
September 3, 2012 - {$177}		1155 balls
3100MHz (100x31)
(3.3GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3450 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT, Turbo)
April 30, 2012 - {$174}		1155 balls
3100MHz (100x31)
(3.5GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3450S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT, Turbo)
April 30, 2012 - {$174}		1155 balls
2800MHz (100x28)
(3.5GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3470 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT, TXT, vPro, Turbo)
June 4, 2012 - {$184}		1155 balls
3200MHz (100x32)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3470S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT, TXT, vPro, Turbo)
June 4, 2012 - {$184}		1155 balls
2900MHz (100x29)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3475S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 4000 GPU)
(EM64T, NX bit, VT, TXT, vPro, Turbo)
June 4, 2012 - {$201}		1155 balls
2900MHz (100x29)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3550 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT, TXT, vPro, Turbo)
April 30, 2012 - {$194}		1155 balls
3300MHz (100x33)
(3.7GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3550S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT, TXT, vPro, Turbo)
April 30, 2012 - {$194}		1155 balls
3000MHz (100x30)
(3.7GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3570 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT, TXT, vPro, Turbo)
June 4, 2012 - {$205}		1155 balls
3400MHz (100x34)
(3.8GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3570K MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 4000 GPU)
(EM64T, NX bit, VT, Turbo)
April 30, 2012 - {$212}		1155 balls
3400MHz (100x34)
(3.8GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3570S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT, TXT, vPro, Turbo)
June 4, 2012 - {$205}		1155 balls
3100MHz (100x31)
(3.8GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i5 3570T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HM-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 2500 GPU)
(EM64T, NX bit, VT, TXT, vPro, Turbo)
April 30, 2012 - {$205}		1155 balls
2300MHz (100x23)
(3.3GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (16-way)		? million
0.022µm process
133mm² die
Core i7 2600 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 3000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$294}		1155 balls
3400MHz (100x34)
(3.8GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		995 million
0.032µm process
216mm² die
Core i7 2600K MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 3000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
January 9, 2011 - {$317}		1155 balls
3400MHz (100x34)
(3.8GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		995 million
0.032µm process
216mm² die
Core i7 2600S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 3000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$306}		1155 balls
2800MHz (100x28)
(3.8GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		995 million
0.032µm process
216mm² die
Core i7 2700K MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 3000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
October 24, 2011 - {$332}		1155 balls
3500MHz (100x35)
(3.9GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		995 million
0.032µm process
216mm² die
Core i7 3770 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HE-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 4000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, vPro, Turbo)
April 23, 2012 - {$278}		1155 balls
3400MHz (100x34)
(3.9GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		1400 million
0.022µm process
160mm² die
Core i7 3770K MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HE-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 4000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
April 23, 2012 - {$313}		1155 balls
3500MHz (100x35)
(3.9GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		1400 million
0.022µm process
160mm² die
Core i7 3770S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HE-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 4000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, vPro, Turbo)
April 23, 2012 - {$278}		1155 balls
3100MHz (100x31)
(3.9GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		1400 million
0.022µm process
160mm² die
Core i7 3770T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge HE-4)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, 650MHz Intel HD 4000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, vPro, Turbo)
April 23, 2012 - {$278}		1155 balls
2500MHz (100x25)
(3.7GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		1400 million
0.022µm process
160mm² die


Core i7 (Socket 2011)
Intel
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Core i7 3820 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-E)
256-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 2xQPI, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
February 14, 2012 - {$294}		2011 balls
3600MHz (100x36)
(3.8GHz Turbo)
(64-bit bus)
?v		Socket 20114x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
10MB on-Die shared L3 (16-way)		2270 million
0.032µm process
435mm² die
Core i7 3930K MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-E)
256-bit DDR3 on-Die unbuffered PC10666 mem controller
(6 cores, 2xQPI, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
November 15, 2011 - {$594}		2011 balls
3200MHz (100x32)
(3.8GHz Turbo)
(64-bit bus)
?v		Socket 20116x 32KB data (8-way)
6x 32KB instruction (8-way)
6x 1.5k µops instruction (8-way)
6x 256KB on-Die unified L2 (8-way)
12MB on-Die shared L3 (16-way)		2270 million
0.032µm process
435mm² die
Core i7 3960X Extreme MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-E)
256-bit DDR3 on-Die unbuffered PC10666 mem controller
(6 cores, 2xQPI, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
November 15, 2011 - {$999}		2011 balls
3300MHz (100x33)
(3.9GHz Turbo)
(64-bit bus)
?v		Socket 20116x 32KB data (8-way)
6x 32KB instruction (8-way)
6x 1.5k µops instruction (8-way)
6x 256KB on-Die unified L2 (8-way)
15MB on-Die shared L3 (16-way)		2270 million
0.032µm process
435mm² die
Core i7 3970X Extreme MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-E)
256-bit DDR3 on-Die unbuffered PC10666 mem controller
(6 cores, 2xQPI, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
November 13, 2013 - {$999}		2011 balls
3500MHz (100x35)
(4.0GHz Turbo)
(64-bit bus)
?v		Socket 20116x 32KB data (8-way)
6x 32KB instruction (8-way)
6x 1.5k µops instruction (8-way)
6x 256KB on-Die unified L2 (8-way)
15MB on-Die shared L3 (16-way)		2270 million
0.032µm process
435mm² die
Core i7 4820K MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge-E)
256-bit DDR3 on-Die unbuffered PC14933 mem controller
(quad core, ?xQPI, SMT Hyperthreading, EM64T, NX bit, VT, vPro, Turbo)
September 9, 2013 - {$323}		2011 balls
3700MHz (100x37)
(3.9GHz Turbo)
(64-bit bus)
?v		Socket 20114x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
10MB on-Die shared L3 (16-way)		1860 million
0.022µm process
257mm² die
Core i7 4930K MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge-E)
256-bit DDR3 on-Die unbuffered PC14933 mem controller
(6 cores, ?xQPI, SMT Hyperthreading, EM64T, NX bit, VT, vPro, Turbo)
September 9, 2013 - {$583}		2011 balls
3400MHz (100x34)
(3.9GHz Turbo)
(64-bit bus)
?v		Socket 20116x 32KB data (8-way)
6x 32KB instruction (8-way)
6x 1.5k µops instruction (8-way)
6x 256KB on-Die unified L2 (8-way)
12MB on-Die shared L3 (16-way)		1860 million
0.022µm process
257mm² die
Core i7 4960X Extreme MMX SSE SSE2 SSE3 SSE4.2 AVX
(Ivy Bridge-E)
256-bit DDR3 on-Die unbuffered PC14933 mem controller
(6 cores, ?xQPI, SMT Hyperthreading, EM64T, NX bit, VT, vPro, Turbo)
September 9, 2013 - {$999}		2011 balls
3600MHz (100x36)
(4.0GHz Turbo)
(64-bit bus)
?v		Socket 20116x 32KB data (8-way)
6x 32KB instruction (8-way)
6x 1.5k µops instruction (8-way)
6x 256KB on-Die unified L2 (8-way)
15MB on-Die shared L3 (16-way)		1860 million
0.022µm process
257mm² die


Notes:
Current URL: http://www.pchardwarelinks.com/nehalem.htm
Designed by: Chris Hare
© 1997-Present by Chris Hare
Legal Stuff
Last Updated: September/2/2015