[ Main Menu / 586 Processor Pinout ]
321 pins - 19x19 (37x37) Staggered Pin Grid Array - Zero Insertion Force socket or Low Insertion Force socket.
Bottom view of the processor (pin side). Pin One is in the lower left corner.
The 'x' pin shows the location of the KEY pin on the processor. Only the AMD K6 has this feature.
CORE voltage | I/O voltage
plane (Vcc2) | plane (Vcc3)
|
1 3 5 7 9 11 13 15 17 19 |21 23 25 27 29 31 33 35 37
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
|----------------------------------------|----------------------------------|
AN | o o o o o o o o o o |o o o o o o o o o | AN
AM | o o o o o o o o o o| o o o o o o o o | AM
AL | o o o o o o o o o o__|o o o o o o o o o | AL
AK | o o o o o o o o o| o o o o o o o o o | AK
AJ | o o o o o o o o o |o o o o o o o o o o | AJ
AH | o o ---------------------|----------------------- x o o | AH
AG | o o o / | \ o o o | AG
AF | o o / | \ o o | AF
AE | o o o | | | o o o | AE
AD | o o | | | o o | AD
AC | o o o | | | o o o | AC
AB | o o | | | o o | AB
AA | o o o | | | o o o | AA
Z | o o | | | o o | Z
Y | o o o | | | o o o | Y
X | o o | | | o o | X
W | o o o | | | o o o | W
V | o o | BOTTOM VIEW | o o | V
U | o o o | (pin side) | o o o | U
T | o o | | | o o | T
S | o o o | | | o o o | S
R | o o | | | o o | R
Q | o o o | | | o o o | Q
P | o o | | | o o | P
N | o o o | | | o o o | N
M | o o | | | o o | M
L | o o o | | | o o o | L
K | o o | | | o o | K
J | o o o | | | o o o | J
H | o o \ | / o o | H
G | o o o \ | / o o o | G
F | o o o ---------------------|----------------------- o o | F
E | o o o o o o o o o |o o o o o o o o o o | E
D | o o o o o o o o o| o o o o o o o o o | D
C | o o o o o o o o o |o o o o o o o o o o | C
B | o o o o o o o o o| o o o o o o o o o | B
A \ o o o o o o o o |o o o o o o o o o o | A
\----------------------------------|--------------------------------------|
1 3 5 7 9 11 13 15 17 |19 21 23 25 27 29 31 33 35 37
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
|
CORE voltage | I/O voltage
plane (Vcc2) | plane (Vcc3)
The chart is available online in HTML format: 586PIN2.HTM. Be aware that it is a large chart and may take a few seconds to load.
The chips included are:
Only Socket 5 and Socket 7 compatible chips are listed. No 486 processors are here. Neither are the Socket 4 Pentium 60 and 66 nor their Pentium OverDrive processors (120 and 133MHz - P5T). The Pentium Pro, Pentium II, Celeron, and Xeon also have their own unique connection to the motherboard, and so are not listed.
| A3 - A31 | Address pins. |
| A20M# | Address bit 20 Mask pin. |
| ADS# | Address Status. |
| ADSC# | Cache Address Strobe. Functionally the same as ADS#. |
| AP | Address Parity. |
| APCHK# | Address Parity Check. |
| BE0# - BE7# | Byte Enable pins. |
| BF0 - BF2 | Bus Frequency clock multiplier (bus to core frequency ratio). 1.5x and 2.0x when only BF0 is present. 1.5x, 2.0x, 2.5x, and 3.0x when BF0 and BF1 are present. 2.0x, 2.5x, 3.0x, 3.5x, 4.0x, 4.5x, 5.0x, and 5.5x when BF0, BF1, and BF2 are present. [ Note: What multipliers are available is entirely dependent on the processor itself. ] |
| BOFF# | Backoff input. |
| BRDY# | Burst Ready. |
| BRDYC# | Cache Burst Ready. Functionally the same as BRDY#. |
| BREQ | Bus Request. |
| BUSCHK# | Bus Check. |
| CACHE# | Cache. |
| CLK | Clock input. Provides fundamental timing for the processor. |
| D/C# | Data/Code. Primary bus cycle definition pin. |
| D0 - D63 | Data pins. |
| DP0 - DP7 | Data Parity pins. |
| EADS# | External Address. |
| EWBE# | External Write Buffer Empty. |
| FERR# | Floating Point Error. |
| FLUSH# | Cache flush. |
| HIT# | Hit. Reflects the outcome of an inquire cycle. |
| HITM# | Hit to a Modified line. Reflects outcome of an inquire cycle. |
| HLDA | Bus Hold Acknowledge. |
| HOLD | Bus Hold request. |
| IERR# | Internal Error. Indicates parity or functional redundancy errors. |
| IGNNE# | Ignore Numeric Error. |
| INIT | Processor Initialization pin. |
| INTR/LINT0 | Active maskable Interrupt. If APIC is enabled, this becomes LINT0. |
| INV | Invalidation. Determines final cache line state. |
| KEN# | Cache Enable. |
| LOCK# | Bus Lock. Indicates that the current bus cycle is locked. |
| M/IO# | Memory Input-Output. Primary bus cycle definition pin. |
| NA# | Next Address. Indicates external memory system is ready to accept a new bus cycle. |
| NMI/LINT1 | Non-Maskable Interrupt. If APIC is enabled, this becomes LINT1. |
| PCD | Page Cache Disable. |
| PCHK# | Parity Check. |
| PEN# | Parity Enable. |
| PM0 - PM1 | Performance Monitoring pins. Can also act as BreakPoint pins BP0 and BP1. |
| PRDY | Probe Ready. |
| PWT | Page Write Through. |
| R/S# | Run/Stop. Places processor in an idle state. |
| RESET | Reset. |
| SCYC | Split Cycle. |
| SMI# | System Management Interrupt. Allows processor to enter System Management Mode. |
| SMIACT# | System Management Interrupt Active. Indicates that processor is in System Management Mode. |
| STPCLK# | Stop Clock. Stops internal clock of processor causing core to consume less power. |
| TCK | Testability Clock. Used to clock state information and data into and out of the processor during boundary scan. |
| TDI | Test Data Input. Serial input for the test logic. |
| TDO | Test Data Output. Serial output for the test logic. |
| TMS | Test Mode Select. |
| TRST# | Test Reset. |
| Vcc2DET | Vcc2 Detect. Identifies processor that require a lower core voltage. |
| W/R# | Write/Read. Primary bus cycle definition pin. |
| WB/WT# | Write Back/Write Through. Allows data cache to be defined as write-back or write-through. |
| KEY | Key pin. Non-functional pin to prevent CPU insertion into a Socket 5 motherboard. |
| Vcc2H/L# | Identifies core voltage of the K6 processor (model 7, 8, and 9 chips). AMD states: "Upon sampling VCC2DET Low to identify dual-voltage processor requirements, system logic should sample Vcc2H/L# to identify the core voltage requirements for 2.9v and 3.2v products (High) and 2.2v products (Low)." |
| BHOLD | Scatter/Gather Interface pin. 6x86 processor only. |
| CLKMUL | Clock Multiplier pins (Bus Frequency). 2.0x and 3.0x for 6x86 and 6x86L. 2.0x, 2.5x, 3.0x, and 3.5x for 6x86MX. |
| DHOLD# | Scatter/Gather Interface pin. 6x86 processor only. |
| LBA# | Scatter/Gather Interface pin. 6x86 processor only. |
| QDUMP# | Scatter/Gather Interface pin. 6x86 processor only. |
| SUSP# | Suspend Request. Requests that the processor enters suspend (low power) mode. |
| SUSPA# | Suspend Request Acknowledge. Acknowledges that the processor is in suspend mode. |
| Vcc2H/L# | Identifies core voltage of the newer MII processors (works the same as the AMD K6). AMD states: "Upon sampling VCC2DET Low to identify dual-voltage processor requirements, system logic should sample Vcc2H/L# to identify the core voltage requirements for 2.9v and 3.2v products (High) and 2.2v products (Low)." |
| WM_RST# | Warm Reset. A reset where the data held in the cache remains intact. |
| BP2 - BP3 | BreakPoint pins. |
| CPUTYP | CPU Type. Distinguishes primary processor from secondary. |
| D/P# | Dual/Primary processor indication. |
| FRCMC# | Functional Redundancy Checking Master/Checker. Determines whether processor is configured as master or checker. |
| LINT0/INTR | Local Interrupt 0. If not under APIC, becomes INTR. |
| LINT1/NMI | Local Interrupt 1. If not under APIC, becomes NMI. |
| PBGNT# | Private Bus Grant. Grant line to to perform arbitration between dual processors. |
| PBREQ# | Private Bus Request. Request line to perform bus arbitration between dual processors. |
| PHIT# | Private Hit. Maintains local cache coherency in the presence of dual processors. |
| PHITM# | Private Modified Hit. Maintains local cache coherency in presence of dual processors. |
| PICCLK | Programmable Interrupt Controller Clock. |
| PICD0 [DPEN#] | Dual Processing Enable. |
| PICD1 [APICEN] | Advanced Programmable Interrupt Controller Enable. Enables or disables APIC interrupt controller. |